1. Field of the Invention
The present invention relates to a wafer acceptance testing(WAT) method, and more particularly, to a WAT method for monitoring gate conductor-deep trench (GC-DT) misalignment and a test key structure used in this method.
2. Description of the Prior Art
In semiconductor fabrication, a semiconductor device or an integrated circuit (IC) should be continuously tested in every step so as to maintain device quality. Usually, a testing circuit is simultaneously fabricated with an actual device so that quality of the actual device can be judged by a performance of the testing circuit. The quality of the actual device therefore can be well controlled. Typically, such testing circuit, which is also referred to as “test key”, is disposed on peripheral area of each chip or die.
Please refer to FIG. 1 and FIG. 2. FIG. 1 is an enlarged top view of a part of a conventional test key layout for monitoring GC-DT (Gate Conductor-Deep Trench) misalignment during the fabrication of deep trench capacitors of a trench capacitor DRAM device. FIG. 2 is a schematic cross-sectional diagram showing the test key structure along line N—N of FIG. 1. As shown in FIG. 1, the test key layout 1 is fabricated on a silicon substrate 10, usually within a scribe line area. The test key layout 1 comprises two adjacent deep trench capacitors 11 and 12 electrically connecting to each other through out diffusions 30 therebetween. The deep trench capacitors 11 and 12 of the test key layout 1 are fabricated simultaneously with those deep trench capacitors arranged in the memory array using the same fabrication processes. Therefore, the structure of each of the deep trench capacitors 11 and 12 and the structure of each of the deep trench capacitors in the memory array are substantially the same. Basically, as best seen in FIG. 2, each of the deep trench capacitors 11 and 12, which are embedded into a main surface of the silicon substrate 10, comprises a buried plate 111, a capacitor dielectric 112, storage node 113, and oxide collar 114. The storage node 113 of the deep trench capacitor 11 and the storage node 113 of the deep trench capacitor 12 are electrically connected to each other through the overlapping out diffusions 30. A cap insulation layer 115 is disposed atop each of the deep trench capacitors 11 and 12. A plurality of gate conductor (GC) lines overlays the deep trench capacitors 11 and 12. As specifically indicated in FIG. 1, these GC lines are alternately denoted by “T” and “B”, wherein “T” stands for a top GC line (GC-T) and “B” stands for a bottom GC line (GC-B). The plurality of GC lines including GC-T and GC-B are arranged in column on the main surface of the silicon substrate 10. The GC-B 201 is disposed at one side of the deep trench capacitor 11. The GC-T 202 runs over the deep trench capacitor 11. The GC-B 203 runs over the deep trench capacitor 12. The GC-T 204 is disposed at one side of the deep trench capacitor 12.
As best seen in FIG. 2, the GC-B 201 acts as a switching transistor of the deep trench capacitor 11. The GC-T 204 acts as a switching transistor of the deep trench capacitor 12. Heavily doped source/drain 301 is implanted into the silicon substrate 10 at both sides of each of the GC-B 201 and GC-T 204. According to the prior art method, to assess the GC-DT misalignment, the threshold voltage (VTH) shifts of the GC-B 201 and GC-T 204 are measured as known to those skilled in the art. However, the prior art GC-DT misalignment evaluation method is not accurate because there are so many factors affecting the threshold voltages shift of the GC-B 201 and GC-T 204. Some of these factors include narrow GC line width, thermal budget of ion implantation, and GC sidewall etching. Therefore, it is difficult for an inspector to judge the GC-DT misalignment merely according to the measured threshold voltage shift data. Consequently, there is a need to provide an improved wafer acceptance testing method for accurately monitoring GC-DT misalignment.